This invention relates to bipolar transistor structures, and more particularly structures with reduced parasitic capacitance and methods of manufacture thereof.
FIG. 1 is a cross section of prior art Vertical Bipolar Transistor formed on a silicon semiconductor substrate. The transistor includes a doped emitter E, a doped collector C and a counterdoped compound base, in accordance with conventional bipolar device design. The collector C is formed between a pair of Shallow Trench Isolation (STI) (dielectric) regions in the surface of the silicon semiconductor substrate. The compound base comprises an intrinsic silicon (Si) or silicon-germanium (Si—Ge) base region and an extrinsic base region thereabove. The doped intrinsic base region, overlies the collector C and enclosed by the emitter area is in mechanical and electrical contact with the collector and emitter regions. The extrinsic base region overlies the outer surfaces of the intrinsic base region and portions of the STI regions. The emitter region is formed above the intrinsic base and is separated from the extrinsic base by dielectric regions. The Base-to-Collector Capacitance (Ccb) of the device is the sum of the components between (1) the base and the collector inside the active area (defined by the emitter opening) (2) the base and the collector outside the active area, but inside the STI edge (3) the base and the collector across the STI region.
Cut-off frequency (fT) and maximum oscillation frequency (fmax) are the most representative measures of operation speed for high-speed transistors. Hence, the design and optimization efforts for the high-speed transistors are mostly directed toward the maximization of these two parameters. One of the device parameters that influences the cut-off frequency (fT) and maximum oscillation frequency (fmax) is the Base-to-Collector capacitance (Ccb). The value of fT decreases with increasing Ccb as a result of increasing RC delay (charging time) associated with emitter and collector resistances and device transconductance. The impact of Ccb on fmax is even larger as fmax is more sensitive to RC delay associated with Ccb. Overall, the device component (resistance and capacitance) that has the largest impact on fT and fmax, or device operation speed, is Ccb. Therefore, the most effective way to improve device speed through parasitic component reduction is the minimization of extrinsic component of Ccb.
The extrinsic component, or parasitic component, of Ccb comprises more than half of the total Ccb for most conventional bipolar transistors. This parasitic capacitance results from the overlap between the collector and base (intrinsic and extrinsic) regions outside the active transistor area and extending over the shallow trench isolation (STI). The overlap between these regions can not be minimized by lithography due to limitation of overlay and alignment tolerances imposed by the requirement to minimize dimensions and increase the density of devices on the substrate. Moreover, the parasitic capacitance is further increased by the diffusion of the dopants from the base region to the collector region. Therefore, structural optimization of the device which would reduce the parasitic component is a key for the improvement of fT and fmax (i.e. the operation speed of the device).
U.S. Pat. No. 5,599,723 Sato Feb. 4, 1997 entitled “Method for Manufacturing Bipolar Transistor Having Reduced Base-Collector Parasitic Capacitance” teaches use of SiGe for the base, and that the parasitic capacitance formed between the collector epitaxial layer and the base electrode single crystal silicon film is reduced because the distance between them is set to about 1000 Å. In order to reduce the parasitic capacitance by the prior art technique, the intrinsic base must be thickened, and thus the cut-off frequency fT is lowered. A single crystal form of silicon formed by the selective epitaxial growth is used for the base electrode to reduce the parasitic capacitance between the base and the collector, particularly by forming the base of SiGe. The entire device including the collector regions is formed above the surface of the silicon semiconductor substrate. The approach to reducing the parasitic capacitance is to use selective epitaxy to grow the intrinsic base.
U. S. Pat. No. 5,128,271 of Bronner et al. entitled “High Performance Vertical Bipolar Transistor Structure via Self-aligning Processing Techniques” describes a self-aligned, vertical bipolar transistor structure and a method of manufacturing such a structure with “reduced parasitic base collector capacitance” achieved by providing correct alignment. The Bronner et al. approach has similarities with the present approach to solution of the parasitic base collector capacitance problem. However, the approach of this invention has significant features not described in the Bronner et al. patent. The present invention decouples the primary STI formation from the self-aligned shallow isolation extension (or secondary shallow isolation) formation to reduce the parasitics. This major difference allows a robust manufacturing process and flexible device performance tailoring in many ways some of which are listed below:
(1) The present invention approach is more compatible with CMOS device fabrication for manufacturing BiCMOS technology, where the STI and the shallow isolation extension are formed independently.
(2) The present invention allows the use of different dielectric material(s), than that used to form the STI, to form the shallow isolation extension to further reduce the capacitance.
(3) The present invention utilizes the STI portion exposed to end-point of the RIE of the intrinsic base and as a self-aligning edge to extend the RIE into the collector pedestal.
(4) The present invention allows partial removal of the collector pedestal, which can be employed to tailor the collector pedestal shape within the STI.
(5) The present invention employs a raised extrinsic base and does not require the partial removal of the STI silicon oxide to form the extrinsic base.